Amid the current AI boom, the demand for advanced semiconductor technology is steadily increasing as chips provide the computing power needed to drive model development and related applications. As mentioned in our previous introduction to CoWoS, besides continuously reducing "gate length" in the future, "advanced packaging" can also enhance chip performance. Below in the article, we will introduce what SoIC packaging is and its potential applications in the future!
Read more introduction about CoWoS here. Taiwan Industry 101: Introduction to CoWoS Technology
What is SoIC Packaging?
SoIC (System-on-Integrated-Chips) is an advanced packaging technology developed by TSMC, focusing on high-density 3D chip stacking. In previous article, we discussed how CoWoS falls under the "2.5D" packaging category, where the lower layer integrates a PCB and an interposer in a vertical (3D) arrangement, while the upper layer consists of horizontally placed SoC chips and HBM (2D), forming a 2.5D structure.
SoIC is the industry's first high-density 3D chiplet stacking technology. What sets it apart is its use of through-silicon vias (TSV) instead of traditional metal bump stacking. TSVs are created using chemical etching or laser drilling, allowing chips to be vertically stacked. This approach reduces reliance on silicon interposers, thereby shrinking the overall stacked package size.
| CoWoS | SoIC | |
|---|---|---|
| Full Name | Chip-on-Wafer-on-Substrate | System-on-Integrated-Chips |
| Packaging Type | 2.5D | 3D |
| Current Adoption | Already in commercial products | Still in testing and development |
However, directly integrating TSVs within chips is highly complex. Additionally, chips and wafers must remain perfectly flat to ensure proper bonding. As a result, the reliability and yield of this technology still require improvement, and it remains in the testing and development stage.
Key Features of SoIC
High-Density Stacking
SoIC aims to achieve a density of 1 million interconnects per square millimeter in the future. Enhanced stacking technology enables greater computational power, faster data transfer rates, and a more compact package. Shorter signal transmission distances also help reduce power consumption.
Bump-less Design
Unlike traditional packaging methods that rely on bumps, SoIC adopts hybrid bonding technology, which enables tighter chip-to-chip connections and improved thermal performance. Hybrid bonding allows for direct copper-to-copper (Cu-Cu) interconnects, eliminating the need for bumps as connectors. This approach increases interconnect density and enhances overall performance.
Currently, SoIC offers two different stacking solutions tailored to various application needs:
1. SoIC - P
Utilizes micro-bump stacking, making it suitable for cost-sensitive products such as mobile devices.
2. SoIC - X
Employs a bump-less stacking approach, designed for high-performance computing applications, making it ideal for AI-related workloads.
Diverse Applications
SoIC technology is compatible with 10nm and below advanced process nodes, offering broad application potential in cloud computing, edge computing, and high-performance computing (HPC). For example, SoIC enhances computational efficiency and bandwidth, addressing the demand for high performance and low latency in cloud computing. Additionally, its high-density interconnects and low power consumption make it an excellent fit for edge computing applications, including autonomous vehicles, augmented reality (AR), and virtual reality (VR), where fast response times are critical.
Market Outlook
As semiconductor technology advances, SoIC is seen as a key trend in future chip design and manufacturing. TSMC plans to begin mass production of SoIC in 2025, with expectations of widespread adoption in high-demand sectors such as autonomous vehicles and AI servers. Overall, SoIC represents a significant leap in packaging technology, enabling substantial performance and efficiency gains while maintaining a compact form factor.
Although SoIC is still in its early pilot production phase, major U.S. tech companies have already started discussions with TSMC on potential collaborations. Reports suggest that AMD’s MI300 series AI GPUs and high-end gaming CPUs, along with Apple’s M5 chips, are expected to adopt SoIC packaging in 2025. Currently, SoIC's monthly production capacity is around 4,000 wafers, with plans to at least double by next year and expand several times over by 2026.
Now that you've gained a solid understanding of SoIC packaging, check out more AI industry-related articles below!
Taiwan Industry 101: Semiconductor
Taiwan Industry 101: Introduction to CoWoS Technology
