As AI computing continues to drive higher demand for processing power, packaging technology is rapidly shifting from mature 2D IC toward 2.5D and 3D IC. However, as packaging integration increases, process challenges are also becoming more complex. First, AI chip power consumption is rising quickly, from around 700W in the Hopper generation to 1,400W in Blackwell, and further to 2,300W in Rubin, pushing traditional packaging and testing tools closer to their physical limits. Second, as the interposer size required for AI chips continues to expand, the geometric limitations of traditional circular wafers are becoming a major bottleneck for mass-production efficiency. Taking a 5.5x reticle-size interposer as an example, a single 12-inch wafer can only yield 9 interposers, while edge waste worsens further as interposer size increases. Therefore, significantly improving effective output per process run without sacrificing yield is the key problem that panel-level packaging aims to solve.

PLP Reshapes Advanced Packaging Processes with Glass Substrates and Large-Size Panels

Panel Level Packaging (PLP) is an advanced packaging technology that replaces traditional circular wafers with large rectangular panels as the packaging substrate. Its core objective is to improve area utilization and packaging output efficiency per process run.

Compared with wafer-level packaging, which is constrained by edge waste from circular wafers and fewer available units as interposer size increases, panel-level packaging uses rectangular substrates to accommodate more packaging units under the same process conditions, thereby lowering unit packaging costs and improving mass-production efficiency. Using the same 5.5x reticle-size example, a 300×300mm rectangular panel can accommodate 16 interposers, around 128% more than the 7 interposers from a 12-inch wafer. The larger the panel size, the more significant the efficiency gain.

Another key difference between PLP and today's mainstream advanced packaging technologies is its gradual adoption of glass materials to replace traditional silicon-based or organic substrates as the packaging platform. The industry's development path can generally be divided into two stages. In the initial stage, glass carriers are used to expand packaging size, improving stability and output efficiency in large-area processes. The next stage will move toward glass interposers and glass core substrates, with the key technology being TGV, or through-glass via technology.

Glass is selected as a substrate material mainly because its physical properties are better suited to large-size and high-density packaging requirements. The coefficient of thermal expansion of glass substrates is around 3 to 9 ppm/°C, significantly lower than the 12 to 20 ppm/°C of organic substrates. This means glass experiences less deformation from temperature changes in large-area processes, helping maintain alignment accuracy for fine circuits. Glass also offers better flatness, supporting line width/spacing below 5/5µm and high-aspect-ratio fine via structures above 5:1, which is important for the high-density interconnects required by AI chips.

However, glass materials also create new process challenges. Because glass is brittle and difficult to process, existing materials, equipment, and process parameters must be redesigned and redeveloped, leaving yield and quality stability highly uncertain. Among these challenges, the TGV process is one of the most critical. After drilling vias in glass, metallization must be completed inside high-aspect-ratio holes. Compared with silicon substrates, however, it is more difficult to form a stable metal adhesion layer on glass surfaces, making metallization and yield control more complex. Measurement also faces bottlenecks. As the number of vias can reach millions and full inspection is required, most current equipment still focuses on surface defect detection, while 3D imaging and measurement capabilities for internal via structures remain limited. In addition, heat generated during equipment operation may affect stage accuracy, and the wide variety of defect types makes defect classification and yield improvement more time-consuming.

AI and HPC to Drive Rapid Future Growth in PLP

According to market research estimates, PLP will become one of the fastest-growing areas in advanced packaging. The PLP market exceeded USD 300 million in 2025 and is expected to expand at a compound annual growth rate of more than 40% from 2025 to 2031, approaching USD 3 billion in market size and entering an accelerated growth phase in 2029.

• At the current stage, PLP applications are still mainly concentrated in consumer electronics, power management ICs, and automotive electronics, with demand primarily coming from consumer products such as smartphones. AI and HPC-related products remain in the early stages of adoption and capacity expansion, with more visible growth expected from the second half of 2026.
• Looking at the medium to long term, UHD Fan-Out and 2.5D Interposer applications will become the main growth engines for PLP market expansion. Mass production for AI-related applications is expected around 2027 and could become the largest revenue source for the PLP market between 2029 and 2031.

Technology Comparison: FOPLP vs. FOWLP

FOPLP (Fan-Out Panel-Level Packaging) and FOWLP (Fan-Out Wafer-Level Packaging) are both Fan-Out packaging architectures in nature. Their core concept is to embed bare dies in molding material and then use RDL to extend chip I/O outward, enabling high I/O density, strong signal integrity, and a substrate-free packaging structure. The biggest difference lies in the carrier format and production model. FOWLP uses circular wafers as the manufacturing platform, while FOPLP uses large rectangular panels.

At present, FOWLP remains the more mature mass-production solution in terms of technical capability and economies of scale, with advantages such as high yield and high-precision RDL. It will remain an important packaging technology for high-end mobile devices and automotive chips over the next five years. However, the value of FOPLP lies in its lower unit cost and potential for large-size packaging. As AI GPUs, chiplets, and CPO package sizes continue to increase, 300mm wafers are gradually approaching their economic efficiency limits. Large rectangular panels can support much larger packaging sizes than wafer-level packaging, while offering higher area utilization and potential cost advantages. As a result, FOPLP is regarded as an important development direction for AI, HPC, chiplets, and next-generation ultra-large advanced packaging markets.

Comparison Item	FOPLP (Fan-Out Panel-Level Packaging)	FOWLP (Fan-Out Wafer-Level Packaging)
Core Concept	RDL is fabricated on a rectangular panel	RDL is fabricated on a reconstituted wafer
Carrier	Rectangular panel	Circular wafer
Mainstream Size	310×310 mm, 510×515 mm, 600×600 mm, etc.	300 mm (12-inch)
RDL Line Width/Spacing (L/S)	Around 5/5 to 10/10 μm, with some moving toward 2/2 μm	Around 2/2 to 5/5 μm
Area Utilization	High, around 85–95% or above	Lower, around 85% or below
I/O Density	Relatively high	High
Cost Structure	Low	High
Mass Production Timeline	Expected to enter rapid capacity expansion around 2025–2030	Mature technology, already in mass production
End Applications	Consumer IC products, automotive applications, and future expansion into AI GPUs, HPC, chiplets, and networking ASICs	AP, RF, PMIC, automotive ICs

Technology Comparison: FOPLP vs. Mainstream Advanced Packaging Technologies

The core feature of FOPLP (Fan-Out Panel-Level Packaging) is the shift from traditional 300mm circular wafers to rectangular panels of 310×310mm or even 700×700mm, improving area utilization, supporting larger package sizes, and lowering unit packaging costs. As a result, FOPLP is viewed as an important candidate for future heterogeneous integration and chiplet architectures. However, current advanced packaging technologies such as FOPLP, CoWoS, CoPoS, and EMIB differ in their technical objectives, process architectures, and application positioning. They must be evaluated based on package size, interconnect density, cost structure, and end-application requirements.

• At present, CoWoS remains the mainstream advanced packaging technology for AI and HPC. Its core advantage lies in the highest interconnect density and signal transmission capability, supporting the high-bandwidth requirements of GPUs paired with HBM. Therefore, it remains the main packaging solution for NVIDIA, AMD, and cloud AI ASICs. By comparison, FOPLP uses large rectangular panels and RDL interconnects, eliminating the need for silicon interposers, TSVs, and some wafer-level processes. This provides lower cost and better area utilization. However, current RDL line width/spacing mostly remains around 5 to 10 μm, still below the high-density interconnect level of CoWoS. As a result, FOPLP is unlikely to replace flagship AI GPU packaging in the near term. That said, as AI GPUs, chiplets, and CPO package sizes continue to expand, FOPLP's advantages in large-size packaging and economies of scale will gradually increase.
• CoPoS can be viewed as a panelized version of CoWoS. Like FOPLP, it uses large rectangular panels to improve output efficiency, but the key difference is that CoPoS retains the interposer architecture, while FOPLP uses RDL to directly complete chip interconnects. Because CoPoS can still provide higher I/O density, signal integrity, and power delivery capability through its interposer, it is more suitable for high-end AI applications such as GPU and HBM integration. Its positioning is focused on high-end AI and HPC markets from the start. FOPLP, by contrast, is still primarily focused on cost-driven consumer, automotive, and networking applications, while gradually extending into high-performance computing.
• EMIB embeds local silicon bridges in organic substrates, providing high-density interconnects only where high-speed transmission is required between chips, striking a balance between performance and cost. The bridge area can reach line width/spacing of around 2/2 μm, with interconnect density and heterogeneous integration capabilities superior to current FOPLP. EMIB is mainly used in high-performance computing and chiplet architectures, with positioning closer to CoWoS rather than directly competing with FOPLP.

Overall, CoWoS remains the best performance solution for AI GPU and HBM packaging today. CoPoS aims to overcome CoWoS limitations in package size and cost through panelization. EMIB supports high-performance heterogeneous integration through localized silicon bridges. In contrast, FOPLP represents a development path centered on cost efficiency, area utilization, and large-panel manufacturing. In the short term, it is unlikely to replace CoWoS, CoPoS, or EMIB in flagship AI chips. However, as RDL scaling, warpage control, and large-panel processes mature, FOPLP is expected to gradually expand from consumer, automotive, and networking markets into AI accelerators, HPC, and large chiplet systems between 2027 and 2030, becoming an important platform within the advanced packaging ecosystem.

Comparison Item	FOPLP	CoWoS	CoPoS	EMIB
Core Concept	RDL is fabricated on a rectangular panel to directly complete chip interconnects without using a silicon interposer	GPU and HBM are integrated on a silicon interposer and then connected to an ABF substrate	Panelized CoWoS, using panels to fabricate interposers while retaining the interposer architecture	Local silicon bridge dies are embedded in the substrate to provide localized high-density interconnects
Carrier	Rectangular glass panel	Circular wafer	Rectangular glass panel	ABF substrate
Mainstream Size	310×310 mm, 510×515 mm, 600×600 mm, etc.	300 mm (12-inch) wafer	310×310 mm	120×120 mm
Interconnect Method	RDL	TSV + silicon interposer + RDL	Panel interposer + RDL	Silicon bridge + substrate
Line Width/Spacing (L/S)	Around 5/5 to 10/10 μm, moving toward 2/2 μm	Around 0.8/0.8 to 2/2 μm, depending on CoWoS subtype	Around 0.5/0.5 to 2/2 μm, depending on panel interposer technology	Around 2/2 μm in the bridge area
I/O Density	High, but limited by RDL line width	Highest	Extremely high, close to CoWoS	Extremely high, localized
Signal Integrity	Good	Best	Close to CoWoS	Excellent
Cost Structure	Lowest	Highest	Medium-high	Medium-high
Main Advantages	Large size, low cost, high area utilization	Highest bandwidth, highest I/O density, best signal integrity	Combines CoWoS-level performance with panel-level cost advantages	Localized high-speed interconnects, reduced silicon usage, strong heterogeneous integration capability
Main Limitations	Warpage control, RDL scaling, yield challenges	High cost, expensive interposer, capacity constraints	Panel interposer yield and glass substrate maturity	Limited bridge locations, complex design, still high cost
Mass Production Timeline	Already in mass production; rapid expansion expected from 2025 to 2030	Already in mass production	Mass production expected in 2028	Internal products entered mass production in 2017; no PLP mass production yet for external customers