As AI advances rapidly, global demand for compute is surging. Since 2012, compute required to train AI models has nearly doubled every four months—far outpacing what Moore’s Law can support. This means traditional integrated circuits alone can no longer meet the explosive demand for compute in the AI era.
Against this backdrop, silicon photonics has emerged. Silicon photonics leverages CMOS semiconductor processes to fabricate photonic devices on silicon or silicon-based substrates (e.g., SiGe/Si, SOI), including light emitters, modulators, photodetectors, and optical waveguides. With these components, silicon photonics can efficiently generate, process, and transmit optical signals, significantly boosting data transfer speeds while reducing loss—applicable to optical communications, optical interconnects, and optical computing.
However, silicon photonics still faces material-driven constraints: silicon inherently struggles to densely integrate light sources, and its waveguides and modulators encounter loss and speed bottlenecks. To overcome these challenges, the industry is pushing silicon-based optoelectronic heterogeneous integration. This approach preserves silicon’s mass-production advantages in CMOS manufacturing while incorporating the optoelectronic properties of other materials, enabling higher-performance devices and moving silicon photonics toward true monolithic integration.
Co-Packaged Optics (CPO) Overview
Today’s data centers still primarily use traditional pluggable optical modules. These modules—comprising TOSA, ROSA, light sources, photodetectors, and connectors—are hot-swappable and have long been the standard in optical communications. However, traditional pluggables must carry signals over multiple copper segments during transmission (ASIC → substrate → PCB → inside the module), which causes severe loss at high speeds: at 200G, loss can exceed 20 dB per meter; at 3.2 Tbps, signal attenuation and thermal issues make operation impractical.
CPO addresses these bottlenecks by integrating electronic ICs (EIC) and photonic ICs (PIC) directly into the switch ASIC package, bringing optics much closer to the core chip (e.g., the ASIC) and shrinking the electrical path from centimeters to millimeters. This design dramatically reduces signal attenuation and crosstalk, delivering breakthroughs in bandwidth, power, and space efficiency.
Compared with traditional modules, CPO offers:
- Higher performance: supports higher-speed, higher-capacity transmission.
- Better energy efficiency: according to Cisco, by eliminating high-power DSPs and using low-power SerDes, system power can drop 25%–30%, with ASIC connectivity power cut by up to half.
- Miniaturization & thermal gains: smaller footprint, better airflow, lower system temperatures and fan power.
- Cost advantages: more economical at high-density deployments.
That said, CPO has challenges: failure is harder to service, and the industry lacks unified standards. The sector expects CPO to gradually become mainstream around 2027.
CPO Key Architecture
1. Silicon Optical Engine (OE)
The silicon optical engine (OE) is the core for electro-optic conversion inside a CPO switch. Using 3D packaging, it stacks and integrates lasers, detectors, modulators, and other optical components within the same package as the ASIC. Compared with 2D/2.5D, this tighter integration minimizes signal loss and power consumption.
2. External Laser (ELS)
In CPO systems, embedded lasers are sensitive to time and temperature and cannot be repaired after failure—requiring replacement of the entire optical engine and raising maintenance costs. As a result, many vendors adopt external-laser designs such as the External Laser Small Form-Factor Pluggable (ELSFP), placing the laser in a module that injects light into the CPO silicon photonics for modulation. If the laser fails, the module can be swapped to lower CPO maintenance costs. The interface is specified by the OIF, and standardization helps reduce costs and expand the market.
3. Fiber Array Unit (FAU)
Precise optical alignment between the PIC and FAU is one of the most critical steps in CPO. As channel counts rise and die areas grow, alignment difficulty increases sharply. FAUs typically use V-groove substrates to hold multi-fiber arrays: bare fibers are seated in V-grooves, clamped, glued, and then polished for high precision. In ELSFP systems, when light exits the PIC into fiber, it must first be aligned and coupled through the FAU to ensure efficient, stable transmission.
4. Polarization-Maintaining Fiber (PMF)
Standard fiber can develop birefringence from stress or bending during production, altering the polarization state. PMF uses a specially designed core to enhance birefringence and counter external stress effects. In high-power ELS applications (over 100 W), portions of the CPO switch’s fiber runs require PMF to ensure stable single-polarization transmission. For cost reasons, CPO typically uses PMF on the input side, while the output side uses conventional (lower-cost) fiber.
5. MPO Connectors
CPO switches require extensive internal fiber routing. Unlike single-fiber connectors, MPO is a high-density, multi-fiber connector supporting 8 to 144+ fibers, greatly reducing space and complexity, hence its widespread use in data center interconnects. While CPO shortens the distance between the optical engine and the switch ASIC, it increases routing between the optical engine and the chassis front panel. Thus, high-fiber-count MPOs are commonly used inside CPO to cut front-panel port counts. Looking ahead, CPO switches may even adopt polarization-maintaining MPO. However, PM-MPO must simultaneously align all channels on the MT ferrule, which is technically demanding and raises ASPs.
6. Shuffle Box
Optical signals inside the switch typically enter via an MPO interface, then a splitter box divides them into four paths to four different switch chips. This partitions sources to minimal units for subsequent processing. Ultimately, traffic aggregates at the CX8 network card. The shuffle box is critical in this flow, allocating and conditioning signals to ensure efficient and precise transmission.
In practice—using NVIDIA’s Quantum-X Photonics InfiniBand as an example—electrical signals from the switch chip are first converted to optical via a modulator and then fed into the OE module. Next, the signal is aligned through the FAU and delivered to the MPO interface. From there, light takes two routes: one portion goes over standard fiber to MPO ports on the switch front panel; the other travels over PMF to the front-panel ELS external laser interface.
CPO Related Companies
Broadcom
Since its first CPO switch in 2022 with Tomahawk 4 (25.6 Tbps), Broadcom has significantly reduced power through opto-electronic integration. In 2024, it launched the Bailly switch with Tomahawk 5 (51.2 Tbps) at 5.5 W/800G, supporting multi-rate and large-scale port configurations; it also introduced TWMZM modulators and FOWLP packaging to further boost interconnect performance. In 2025, Broadcom unveiled Tomahawk 6 (102.4 Tbps) with 100G/200G SerDes and CPO support to meet AI networking needs for high performance, low power, and tight system integration—reinforcing its leadership in data center networking.
Marvell
Marvell has pursued CPO since 2022. At OFC 2022, it demonstrated a 3.2T CPO platform prototype for 51.2T switches. In 2024, Marvell announced the industry’s first 3D SiPho optical engine supporting 200 Gbps electrical/optical interfaces—a key module for integrating CPO into XPUs. In January 2025, Marvell said that, based on its latest HBM architecture, it can help customers seamlessly integrate CPO into next-gen custom XPUs, evolving connectivity from in-rack copper links to optical links spanning hundreds of XPUs across racks—greatly enhancing AI server performance and scalability.
NVIDIA
At GTC 2025, NVIDIA introduced Quantum-X and Spectrum-X co-packaged silicon photonics, alongside three new switches: Quantum 3450-LD, Spectrum SN6810, and Spectrum SN6800. Quantum-X, built on InfiniBand, targets HPC and AI supercomputing and is slated for late-2025 availability. Spectrum-X, based on Ethernet, targets cloud and hyperscale data centers and is expected in 2026.
TSMC
In January 2025, TSMC successfully validated the key CPO component microring modulator (MRM) on 3nm and integrated it with advanced packaging. It plans to mass-produce 1.6 Tbps optoelectronic devices in the second half of this year, with initial customers likely including Broadcom and NVIDIA. TSMC is also developing the COUPE (Compact Universal Photonics Engine) technology, using SoIC-X stacking to integrate ICs directly on PICs, substantially lowering interconnect impedance and outperforming traditional packaging—showcasing steady advances in optoelectronic heterogeneous integration.
COUPE will roll out in three phases:
- Gen 1: integrated into OSFP pluggables at 1.6 Tbps, surpassing current copper-based Ethernet (max 800 Gbps).
- Gen 2: integrated as CPO into CoWoS, boosting to 6.4 Tbps and reducing latency.
- Gen 3: further integrating COUPE into the CoWoS interposer for 12.8 Tbps, bringing optics closer to the processor; this is exploratory with no firm timeline.
CPO Applications
IT & Telecom
With high speed and low power, silicon photonics is set to play a major role in IT. In 5G, it already supports base stations and transport, delivering faster electro-optic conversion and energy-efficient links for high performance and reliability. Looking to 6G, its potential for Tbps-class rates and microsecond-level latency can underpin ultra-HD media, AR/VR, and autonomous driving, and advance distributed and self-organizing network architectures. Overall, silicon photonics is becoming a foundational technology for next-gen communications and edge computing, with far-reaching impact on AI and high-bandwidth use cases.
Data Centers
Traditional data centers face chronic challenges: high energy consumption, heavy thermal loads, and bandwidth ceilings. Silicon photonics offers high-speed, low-power interconnects—especially for server-to-server and rack-scale optical links. This not only meets surging bandwidth needs but also significantly improves performance and energy efficiency, making it a key driver of next-generation data center architectures.
Sensors
Silicon photonics is expanding into automotive and immersive applications. In vehicles, it enables higher-precision 3D sensing via LiDAR and improves intra-vehicle data links—enhancing ADAS upgrades and even supporting high-speed V2X communications. Mobileye showcased a silicon-photonics LiDAR SoC at CES 2021 using on-chip FMCW and plans to deploy it in autonomous vehicles starting in 2025—a concrete step for silicon photonics in automotive and smart sensing.
Biotech & Healthcare
Thanks to high integration density and miniaturization, silicon photonics is moving quickly into healthcare. Beyond biosensors that enhance optical diagnostics and imaging accuracy and efficiency, it is well-suited for implantable medical devices. By integrating waveguides, modulators, and photodetectors, silicon photonics can substantially improve medical imaging, tomography, and gene sequencing—becoming a key enabler of precision medicine and next-generation medical technologies.
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